ISLA118P50IRZ【PDF 9/34 页】IC ADC 8BIT SPI/SRL 500M 72QFN

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ISLA118P50

FN7565.2

July 25, 2011

Voltage Reference

A temperature compensated voltage reference provides the

reference charges used in the successive approximation

operations. The full-scale range of each A/D is proportional to the

reference voltage. The nominal value of the voltage reference is

1.25V.

Digital Outputs

Output data is available as a parallel bus in LVDS-compatible or

CMOS modes. In either case, the data is presented in double data

rate (DDR) format. Figures 3 and 4 show the timing relationships

for LVDS and CMOS modes, respectively.

Additionally, the drive current for LVDS mode can be set to a

nominal 3mA or a power-saving 2mA. The lower current setting

can be used in designs where the receiver is in close physical

proximity to the A/D. The applicability of this setting is

dependent upon the PCB layout, therefore the user should

experiment to determine if performance degradation is

observed.

The output mode and LVDS drive current are selected via the

OUTMODE pin as shown in Table 1.

The output mode can also be controlled through the SPI port,

which overrides the OUTMODE pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 22.

An external resistor creates the bias for the LVDS drivers. A 10k

Ω,

1% resistor must be connected from the RLVDS pin to OVSS.

Over Range Indicator

The over range (OR) bit is asserted when the output code reaches

positive full-scale (e.g., 0xFFF in offset binary mode). The output

code does not wrap around during an over-range condition. The

OR bit is updated at the sample rate.

Power Dissipation

The power dissipated by the ISLA118P50 is primarily dependent

on the sample rate and the output modes: LVDS vs CMOS and

DDR vs SDR. There is a static bias in the analog supply, while the

remaining power dissipation is linearly related to the sample

rate. The output supply dissipation changes to a lesser degree in

LVDS mode, but is more strongly related to the clock frequency in

CMOS mode.

Nap/Sleep

Portions of the device may be shut down to save power during

times when operation of the A/D is not required. Two power saving

modes are available: Nap, and Sleep. Nap mode reduces power

dissipation to less than 164mW and recovers to normal operation

in approximately 2.75s. Sleep mode reduces power dissipation to

less than 6mW but requires approximately 1ms to recover from a

sleep command.

Wake-up time from sleep mode is dependent on the state of

CSB; in a typical application CSB would be held high during sleep,

requiring a user to wait 150s max after CSB is asserted

(brought low) prior to writing ‘001x’ to SPI Register 25. The

device would be fully powered up, in normal mode 1ms after this

command is written.

Wake-up from Sleep Mode Sequence (CSB high)

Pull CSB Low

Wait 150s

Write ‘001x’ to Register 25

Wait 1ms until A/D fully powered on

In an application where CSB was kept low in sleep mode, the

150s CSB setup time is not required as the SPI registers are

powered on when CSB is low, the chip power dissipation increases

by ~ 15mW in this case. The 1ms wake-up time after the write of a

‘001x’ to register 25 still applies. It is generally recommended to

keep CSB high in sleep mode to avoid any unintentional SPI

activity on the A/D.

All digital outputs (Data, CLKOUT and OR) are placed in a high

impedance state during Nap or Sleep. The input clock should

remain running and at a fixed frequency during Nap or Sleep, and

CSB should be high. Recovery time from Nap mode will increase

if the clock is stopped, since the internal DLL can take up to 52s

to regain lock at 250MSPS.

By default after the device is powered on, the operational state is

controlled by the NAPSLP pin as shown in Table 2.

The power-down mode can also be controlled through the SPI

port, which overrides the NAPSLP pin setting. Details on this are

contained in “Serial Peripheral Interface” on page 22. This is an

indexed function when controlled from the SPI, but a global

function when driven from the pin.

Data Format

Output data can be presented in three formats: two’s

complement, Gray code and offset binary. The data format is

selected via the OUTFMT pin as shown in Table 3.

TABLE 1. OUTMODE PIN SETTINGS

OUTMODE PIN

MODE

AVSS

LVCMOS

Float

LVDS, 3mA

AVDD

LVDS, 2mA

TABLE 2. NAPSLP PIN SETTINGS

NAPSLP PIN

MODE

AVSS

Normal

Float

Sleep

AVDD

Nap

TABLE 3. OUTFMT PIN SETTINGS

OUTFMT PIN

MODE

AVSS

Offset Binary

Float

Two’s Complement

AVDD

Gray Code

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